Design Center

Host Bus Adapter (HBA) Verification with Trek
A tool like Trek from Beker Verification Systems can speed Verification of a Host Bus Adapter.

• Low Power Design For Analog/Mixed-Signal IP

• PCB Tools Vendors Reference Chart

• Software-Defined Radio Platforms

• Serial ATA and the evolution in data storage technology

• Multi-language Functional Verification Coverage for Multi-site Projects

Learning Center

Most Recent Courses

• IBM is the Clear Choice for EDA Computing
  Technology course  60 min.
• Electromagnetic Noise Reduction Techniques: Part 1
  Technology course  30 min.
• Electromagnetic Noise Reduction Techniques: Part 2
  Technology course  25 min.
• Silicon Tuner Training
  Product course  50 min.
• EMC for ICs
  Technology course  2 hours 15 min.
• sVM—System Verification Methodology
  Product course  45 min.
• Migration to Linux on Intel for EDA Tools Environments
  Lecture  30 min.

Product Center

Latest Product Articles

• Ceva Unveils New Platforms
• Chipvision Delivers ESL Power-Optimization Tools
• Agilent Technologies Released GoldenGate 4.2
• Berkeley Design Automation Delivers Noise Analysis Tool
• Cadence Strengthens Custom IC Design Tools
• Cadence Speeds Analog and Mixed-Signal Verification

Under the Hood

• Under the Hood: Silicon in autos driving patent plans
• Under the Hood: Inside the Apple iPhone
• Under the Hood update: Software at heart of iPhone's simplicity
• DRAM makes move to copper
• Inside Intel's 65-nm NOR flash
• 65 nm: Where are the chips?

Reference Designs

• Broadcom and Avago Technologies Announce Advanced Features and New Price Points to Drive Bluetooth® Laser Mouse Products
• Fujitsu developer kit for fingerprint identification

Technical Paper Library

Latest Technical Papers

• Designing RF, Analog and Digital on PCB
• Preserving Freedom of Choice When Designing FPGAs
• Achieving Quality and Traceability in FPGA/ASIC Flows for DO-254 Aviation Projects
• The Use of Advanced Verification Methods to Address DO-254 Design Assurance
• Domain-Specific Modeling with MetaEdit+: 10 Times Faster Than UML
• Model-Based Methods Critical for Effective Manufacturing-Aware Physical Design
• Clock Domain Crossing Demystified: The Second Generation Solution for CDC Verification

Featured Technical Papers

• Power Hungry? Strategies to Trim Your Chip's Appetite...
  Synopsys
• Clock Domain Crossing Demystified: The Second Generation Solution for CDC Verification
  Real Intent and Sunburst Design
• ZeBu: A Unified Verification Approach for Hardware Designers and Embedded Software Developers
  Emulation and Verification Engineering (EVE)
• Inflexion Platform UI: A New Approach to User Interface Creation for Consumer Electronic Devices
  Mentor Graphics

Webinars

Upcoming Webinars

• May 28, 2008: 
  Co-simulation Enables Efficient Co-Design of WLAN Antenna and Circuitry
  Agilent Technologies

Latest Webinars

• Chip-Package Co-Design: Applying Chip Power Model in System Power Integrity Analysis
  Apache Design Solutions
• Selecting the Optimal Embedded Memory IP Architecture
  Synopsys