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README.md

sv2v (SystemVerilog to Verilog) (via Github Releases) (sv2v)

sv2v converts SystemVerilog (IEEE 1800-2017) to Verilog (IEEE 1364-2005), with an emphasis on supporting synthesizable language constructs.

Example Usage

"features": {
    "ghcr.io/devcontainers-extra/features/sv2v:1": {}
}

Options

Options Id Description Type Default Value
version Select the version to install. string latest

Note: This file was auto-generated from the devcontainer-feature.json. Add additional notes to a NOTES.md.