2
\$\begingroup\$

I was performing a lab experiment in which a JK flip flop is constructed using 7400 Quad 2 input NAND IC and 7410 triple 3 input NAND IC. During toggle mode, a clock signal is given using function generator. During toggle mode, only 1 output keep toggling while the other stays high most of the time and rarely triggers. For example Q keeps toggling and Q' stays high and sometimes when Q' toggles Q stays high always. Initially had 3.3V LEDs with 2.2K resistors at the two outputs which had the described phenomena the resistor values was chosen to eliminate the current source/sink problem of ICs, I then removed those LEDs and just connected the oscilloscope and the waveform still followed what I described. Both the inputs rarely toggles together. However both the inputs almosy toggling together when the input power is around 3V or 2.5V but this is not the prescribed working condition of ICs according to data sheet which says 4.75V - 5.25V as safe operating regime. I did keep decoupling 0.33uF capacitor across power pins of ICs. Tried range of clock frequencies from 1Hz upto 50Hz. What causes this behaviour ?

schematic

Pic Source:- Link

\$\endgroup\$
4
  • \$\begingroup\$ Sounds like a dead chip. Maybe the pullup current caused it to fuse open from a previous wiring fault burning open the low side sink NPN.. \$\endgroup\$ Commented Apr 1 at 13:11
  • \$\begingroup\$ Please "add" a reset for the flip-flops ... \$\endgroup\$ Commented Apr 1 at 17:04
  • \$\begingroup\$ What are your input logic levels? The inputs can't be left floating. \$\endgroup\$ Commented 2 days ago
  • \$\begingroup\$ @MOSFET JK pulled to 5V VCC. CLK to function generator. Q and Q' pulled to ground via a 10K resistor \$\endgroup\$ Commented 2 days ago

6 Answers 6

Reset to default
6
\$\begingroup\$

This circuit is NOT an edge-triggered flip-flop. If J, K and CLK are all high, the circuit will either oscillate or settle in an invalid state with both outputs at intermediate levels (or some combination of the two), depending on the speed of the gates. See the schematic for a 7473 for the internal diagram of a true edge-triggered FF.

\$\endgroup\$
2
\$\begingroup\$

The circuit in the question is prone to racing. If the circuit were constructed in a monolithic circuit, the manufacturer could control the delays in the circuit to ensure proper timing. When you create this circuit, you are responsible for ensuring that the timing is proper.

You would probably have better luck attempting to create a Master-Slave JK flip flop. However, even a Master-Slave JK flip-flop following the typical design of a monolithic circuit is prone to races if implemented with discrete gates.

\$\endgroup\$
2
\$\begingroup\$

Here are two simulations of this circuit, made with microcap v12.

The first circuit (outputs Q1, Q2) is without delays.
The second circuit (outputs Q3, Q4) is with delays (TTL delays).

The first simulation is with [J,K] = [0,0] or [1,0] or [0,1].

enter image description here

The second simulation is with [J,K] anything, included [1,1]

enter image description here

This simulation does clearly shows the "key" for inputs levels.

And here [J,K]=[1,1] ... which shows the internal oscillation when clk=1.
Note that the ideal circuit does not "work".

enter image description here

\$\endgroup\$
2
\$\begingroup\$

There are three types of flip-flops: 1) F-F edge-triggered positive and negative, 2) F-F pulse-triggered (Master-Slave), 3) F-F data lock-out positive and negative. It consists of a master-slave F-F whose clock input has a transition detector and which can be negative or positive. They are further subdivided into S-R, D, J-K, and T.

enter image description here

(The drawings are perfect, but any imperfections are welcome to point out; in fact, thanks in advance.)

\$\endgroup\$
1
\$\begingroup\$

If K & CLK are high & J is low, does Qbar stay low?

If not, chip is bad or has been abused or there are jumper faults.

Wiggle everything and ensure a tight connection is made. Measure V on every pin.

Something is transient.

\$\endgroup\$
1
\$\begingroup\$

This type of latch has a quirk: if botk J and K are high, when the clock is high the output will oscillate.

I've discussed this at length previously:

JK latch, possible Ben Eater error?

Understanding the JK latch

Cures for this behavior include using a master-slave flop (two latches on opposite enables), or using an edge detect circuit to form a very narrow clock pulse.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Start asking to get answers

Find the answer to your question by asking.

Ask question

Explore related questions

See similar questions with these tags.