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I am a first year electrical engineering student, and I am totally confused about how an NMOS transistor actually works.

The idea that a gate source voltage creates a vertical electric field that a current can pass trough horizontally confuses me (I might lack physics intuition) and the fact that it only happens when that voltage is over some “threshold voltage ” and the boundary conditions for saturation being Vds > Vov or Vgd< Vt doesn't make any sense to me.

I have asked my professor about it, and he explained trough this image,

region

but it still doesn’t fit right with me, and I don’t understand the image; it doesn’t feel intuitive.

I am sorry if this is a lot of questions, but my main question is: How does the NMOS operate intuitively and conceptually, preferably with a visual?

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  • \$\begingroup\$ Have you covered surface induction effects yet? MOS capacitor accumulation / depletion / inversion? \$\endgroup\$ Commented Apr 4 at 6:36
  • \$\begingroup\$ The only thing i know is that an inversion layer is formed when Vgs>Vt and when all terminals are grounded, there is a depletion layer. \$\endgroup\$ Commented Apr 4 at 6:56
  • \$\begingroup\$ Check this image out. When Vgs<Vt, that rectangle labeled N isn't there. When Vgs>Vt happens, that N rectangle forms (i.e. "the channel") and connects the two N+ sides together. The N rectangle gets created by the electric field you mention in your question, by attracting electrons upwards from the P-type substrate. This is a simplified view, but hopefully it gives you a starting point to latch onto. Another image: electronicsforu.com/wp-contents/uploads/2023/03/… \$\endgroup\$ Commented Apr 4 at 7:16

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I have written a detailed answer regarding how a BJT works as an amplifer and this will help you understand how a MOSFET (Metal-Oxide-Semiconductor field effect transistor) works. The way NMOS (N-Type MOS) works is very similar to how a NPN Bipolar Junction Transistor (BJT) works. I wont include much of mathematics here, but it will help you to have a physical intuition.

I am taking NPN transistor for my analysis throughout the answer. Before we go into analysis, we know that a standalone N-type semiconductor and standalone P-type semiconductor acts as a conductor as they have free to move charge carriers, electron in N-type and hole in P-type (well P-type has “moving” holes. A forward moving hole can be treated as an electron moving backward, hence having mobility). Basically, the transistor works because we are forcing the sandwich of N-type and P-type wafers to act as a single “uniform” semiconductor, like when a NPN (NMOS) transistor is in ON state, it acts as a single N-type semiconductor, hence conducting electricity (same argument goes for PNP (PMOS) transistor where it acts as a single P-type conductor).

Let's see how a NMOS works. I have simplified most things and avoided as much mathematics as I could do.

Continuing from the quote from my earlier answer, Here is the simplified structure of an NMOS. It is similar to that of a NPN transistor but with a metel-oxide interface as shown. In the images, S is Source, G is Gate, D is drain and S' is "base" terminal.

MOSFET pic

We see that the arrangement is kind of a diode connected back-to-back. So now we see that due to the P-type substrate sharing itself with both drain and source it forms P-N junction on both the sides (red) I have added a diode analogy to the right of the MOSFET figure. The P type is lightly doped. Now have a look at the diode picture, in this way, suppose if we apply a potential difference across source and drain or drain or source, the current won't flow because one diode would always be reverse biased. Recall that a standalone N-type semiconductor is actually a conductor, so how can we make to this N-P-N arrangement as a single N-type semiconductor? If we push electrons into P-type semiconductor, it actually behaves as a N-type semiconductor (Why? because the behavior of the semiconductor type actually depends on the amount of majority charge carriers in it). If one is familiar with a bit of semiconductor physics, you can see this through the Fermi-Dirac derivations. So how to make this N - P - N arrangement behave as a standalone N - type conductor ?

How A Metal-Oxide-Semiconductor (MOS) Capacitor works

Consider a MOS capacitor as shown:-

MOS Capacitor

This is basically a capacitor, the metal and P type substrate acts as conductors seperated by an insulator which in this case is a Silicon Oxide (SiO2). I am not going into details of flat band energy and such but lets see what happens if you apply a potential across G and S. This arrangement has a fairly electrically independent capacitance C_mos which is charge inside it divided by potential applied. We know:-

$$C_{mos} = \frac {Q}{V_{gs}} \implies Q = C_{mos}{V_{gs}}$$

Which means the amount of charge pushed into the plates of capacitor is directly proportional to the Voltage applied across the plates due to the capacitor action by the electric field in inside the substrate. Here the plates are the P Substrate and the Metal. When a potential difference is applied across G and S (with appropriate sign), we pump charge (electrons) into the P substrate which increases the electron concentration inside the P substrate. The behaviour of conductor is dictated majorly by amount and type of charge carriers present in it. Since we pump electrons inside the P substate, all holes are filled by electrons and in fact excess electrons start to accumulate inside the P substrate changing to behavior from P type to N type conductor, more charge you pump, the more N it becomes. This process is called the Inversion. Refer the image below, the change in the type is referred as N' cap

Lets apply this to the MOSFET structure we saw earlier, when a potential difference is applied between G and S' (In almost all mosfets, the S' is shorted to S which reduces number of terminals and makes S as one of the reference for volage, but introduces something called the body diode which you might be knowing), we pump electrons into the P - substrate. We know depletion region is a result of junction formed between P and N semiconductors, since we are changing the behavior of P substrate to N, the excess electrons nulls the holes present in the substrate, which in turn diminishes the depletion layer, slowly making the N - P - N arrangement as a single N conductor. But if you apply the potential between G and S such that there isnt enough charge carriers inside the P - substrate, the diode action persists leaving the MOSFET non conductive. So, we can say that there is a minimum potential difference that needs to be applied across G and S such that the amount of charge pumped inside the substrate is well enough to make substrate conductive by nullifying the depletion region formed otherwise. This voltage is what we call as Threshold Voltage V_th. I am adding images which shows this:- (The slight red signifies the charge pumped inside slowly diminishing the effect of depletion layer). Recall that the substrate is lightly doped, meaning it doesnt take a lot of charge needed to invert it, thus the required Vgs is also considerably small to make it conductive.

mosvth

This is how an NMOS works. same analogy you can apply for PMOS as well.

I am not sure why your professor has given that graph to explain you how a MOSFET works. The graph shows the voltage drop occurs inside the P substrate after inversion, which basically acts as a resistor (which we call as Rds). The potential difference across the channel is uniform only if no current is flowing between S and D. Since the S' in my first image is shorted to S, we can say the potential at S' is equal to S, the potential across the channel is not uniform due to the resistor behavior of channel. The resistance and the voltage drop at distance l from Source is given as where L is total channel length (basically voltage divider):- $$R = \frac {\rho L}{A} \implies V = \frac {V_{DS} l}{L}$$.

question pic

Hence you get a graph like this. Its worth noting though. As the potential between Vgs varies linearly you have to be carful enough to no make the electric field between S and D below the Voltage required to sustain conduction of current. Suppose the potential drop is too much such that at any point in the channel, the electric field would be too weak to hold the charge in the substrate (or channel) as $$Q \propto V_{gs} \implies Q \propto L - l$$ Therefore, we are making the channel prone to depletion due to the potential drop and loses its effective conductance (comes out of saturation, this is what you see in a Id vs Vds graph of a MOSFET. For a given current Id, there must be enough electron concentration in the conductor to conduct electron smoothly, or else voltage starts to build up, making the MOSFET slowly drift into attenuation / linear region, similar to how a BJT works). That means you need more V_gs to make the electric field at that point enough to pump more charge, sustaining hasleless conduction.

All images are made using Google Draw

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    \$\begingroup\$ Thank you for your response, This has cleared up alot for me! \$\endgroup\$ Commented Apr 4 at 17:04
  • \$\begingroup\$ @Jack445 Glad it was helpful :-) \$\endgroup\$ Commented Apr 4 at 17:08
  • \$\begingroup\$ Re "The way NMOS (N-type MOS) works is no different from how an NPN bipolar junction transistor (BJT) works.": That sounds like an oversimplification. \$\endgroup\$ Commented Apr 5 at 13:38
  • \$\begingroup\$ @PeterMortensen OK. Maybe "very similar" should do :-) \$\endgroup\$ Commented Apr 5 at 13:59
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Mr Ishwar has defined the physics well.

Allow me to demonstrate the Enhanced-mode FET behavior compared to a Bipolar Junction Transistor (BJT) using a linear sawtooth with a special case of Vgs=Vds and Vbe=Vce.
Beta is user selected has a convenient calculator link for each FET: >properties.

enter image description here

This simulator is just 1 of dozens created by Paul Falstad based on ideal physics (but without the semiconductor capacitance which is proportional to current rating.) You may find many mouse interactions and built-in circuits. ^z=undo

for @Tim_Williams It is most certainly quadratic above Vt. Here is the same FET with a V-I plot from the same sawtooth enter image description here. The impedance of Vgs=Vds is rather high yet still inverse quadratic relative to Rd=1k.

This quadratic effect on current is more pronounced with Rd=1 ohm I raised the voltage swing to 9.5V well above 250%* Vt(=1.5) so the linear slope of RdsOn on the XY=VI plot is visible above my recommended minimum drive. Ignore the sawtooth retrace. enter image description here

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    \$\begingroup\$ Some of Falstad's simulators are based on idealized physics. The simulator most certainly is not one of them. Not sure offhand what MOS model they use but it's probably something similar to SPICE. Case in point: the curve shown is triangular, not quadratic. \$\endgroup\$ Commented Apr 4 at 15:50
  • \$\begingroup\$ Thanks for this resource! \$\endgroup\$ Commented Apr 4 at 17:04
  • \$\begingroup\$ Tim pls try again to include Rd in your interpretation of current. \$\endgroup\$ Commented Apr 5 at 1:46
  • \$\begingroup\$ @TimWilliams pls delete false statement The physics was defined as shown. with C excluded but can be added discretely. \$\endgroup\$ Commented Apr 5 at 18:05
  • \$\begingroup\$ Oh that's a voltage not a current source! I see. Case still (potentially) in point: where's the subthreshold region? || What C, capacitance? Correctly modeled capacitance is nontrivial to construct from discrete components. || There was an underlying point: there will always and necessarily be room to argue "that's not ideal", for any model; and "ideal physics" implies to me, some kind of "physics-based" or from-principles model, for example simulating the semiconductor material itself; which is quite a bit more challenging than a circuit simulator. \$\endgroup\$ Commented Apr 5 at 18:55

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