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RVA23 Profiles

Table of Contents

RVA23 Profiles

The RVA23 profiles are intended to align implementations of RISC-V 64-bit application processors to allow binary software ecosystems to rely on a large set of guaranteed extensions and a small number of discoverable coarse-grain options. It is explicitly a non-goal of RVA23 to allow more hardware implementation flexibility by supporting only a minimal set of features and a large number of fine-grain extensions.

Only user-mode (RVA23U64) and supervisor-mode (RVA23S64) profiles are specified in this family.

RVA23U64 Profile

The RVA23U64 profile specifies the ISA features available to user-mode execution environments in 64-bit applications processors. This is the most important profile within the application processor family in terms of the amount of software that targets this profile.

RVA23U64 Mandatory Base

RV64I is the mandatory base ISA for RVA23U64 and is little-endian. As per the unprivileged architecture specification, the ECALL instruction causes a requested trap to the execution environment.

RVA23U64 Mandatory Extensions

The following mandatory extensions were present in RVA22U64.

  • M Integer multiplication and division.

  • A Atomic instructions.

  • F Single-precision floating-point instructions.

  • D Double-precision floating-point instructions.

  • C Compressed instructions.

  • B Bit-manipulation instructions.

  • Zicsr CSR instructions. These are implied by presence of F.

  • Zicntr Base counters and timers.

  • Zihpm Hardware performance counters.

  • Ziccif Main memory regions with both the cacheability and coherence PMAs must support instruction fetch, and any instruction fetches of naturally aligned power-of-2 sizes up to min(ILEN,XLEN) (i.e., 32 bits for RVA23) are atomic.

  • Ziccrse Main memory regions with both the cacheability and coherence PMAs must support RsrvEventual.

  • Ziccamoa Main memory regions with both the cacheability and coherence PMAs must support all atomics in the Zaamo extension.

  • Zicclsm Misaligned loads and stores to main memory regions with both the cacheability and coherence PMAs must be supported.

  • Za64rs Reservation sets are contiguous, naturally aligned, and a maximum of 64 bytes.

  • Zihintpause Pause hint.

  • Zic64b Cache blocks must be 64 bytes in size, naturally aligned in the address space.

  • Zicbom Cache-block management instructions.

  • Zicbop Cache-block prefetch instructions.

  • Zicboz Cache-Block Zero Instructions.

  • Zfhmin Half-precision floating-point.

  • Zkt Data-independent execution latency.

The following mandatory extensions are new in RVA23U64:

  • V Vector extension.

Note
 V was optional in RVA22U64.

  • Zvfhmin Vector minimal half-precision floating-point.

  • Zvbb Vector basic bit-manipulation instructions.

  • Zvkt Vector data-independent execution latency.

  • Zihintntl Non-temporal locality hints.

  • Zicond Integer conditional operations.

  • Zimop may-be-operations.

  • Zcmop Compressed may-be-operations.

  • Zcb Additional compressed instructions.

  • Zfa Additional floating-Point instructions.

  • Zawrs Wait-on-reservation-set instructions.

  • Supm Pointer masking, with the execution environment providing a means to select PMLEN=0 and PMLEN=7 at minimum.

RVA23U64 Optional Extensions

Localized Options

The following localized options are new in RVA23U64:

  • Zvkng Vector crypto NIST algorithms with GCM.

  • Zvksg Vector crypto ShangMi algorithms with GCM.

Note
 The scalar crypto extensions Zkn and Zks that were options in RVA22 are not options in RVA23. The goal is for both hardware and software vendors to move to use vector crypto, as vectors are now mandatory and vector crypto is substantially faster than scalar crypto.
Note
 We have included only the Zvkng/Zvksg options with GCM to standardize on a higher performance crypto alternative. Zvbc is listed as a development option for use in other algorithms, and will become mandatory. Scalar Zbc is now listed as an expansion option, i.e., it will probably not become mandatory.
Development Options

The following are new development options intended to become mandatory in a future RVA profile.

  • Zabha Byte and halfword atomic memory operations.

  • Zacas Compare-and-Swap instructions.

  • Ziccamoc Main memory regions with both the cacheability and coherence PMAs must provide AMOCASQ level PMA support.

Note
 Ziccamoc is a new profile-defined extension that ensures Compare and Swap instructions are properly supported in main memory regions. The extension will be added to the PMA section of the privileged architecture manual.

  • Zvbc Vector carryless multiplication.

  • Zama16b Misaligned loads, stores, and AMOs to main memory regions that do not cross a naturally aligned 16-byte boundary are atomic.

Note
 Zama16b is a new profile-defined extension that represents the presence of the new Misaligned Atomicity Granule feature added in Sm1p13. The extension will be added to the PMA section of the privileged architecture manual.
Expansion Options

The following expansion options were also present in RVA22U64:

  • Zfh Scalar half-precision floating-point.

The following are new expansion options in RVA23U64:

  • Zbc Scalar carryless multiply.

  • Zicfilp Landing Pads.

  • Zicfiss Shadow Stack.

  • Zvfh Vector half-precision floating-point.

  • Zfbfmin Scalar BF16 converts.

  • Zvfbfmin Vector BF16 converts.

  • Zvfbfwma Vector BF16 widening mul-add.

Transitory Options

There are no transitory options in RVA23U64.

Note
 Scalar crypto is no longer an option in RVA23U64, though the Zbc extension has now been exposed as an expansion option.

RVA23U64 Recommendations

Implementations are strongly recommended to raise illegal-instruction exceptions on attempts to execute unimplemented opcodes.

RVA23S64 Profile

The RVA23S64 profile specifies the ISA features available to a supervisor-mode execution environment in 64-bit applications processors. RVA23S64 is based on privileged architecture version 1.13.

RVA23S64 Mandatory Base

RV64I is the mandatory base ISA for RVA23S64 and is little-endian. The ECALL instruction operates as per the unprivileged architecture specification. An ECALL in user mode causes a contained trap to supervisor mode. An ECALL in supervisor mode causes a requested trap to the execution environment.

RVA23S64 Mandatory Extensions

The following unprivileged extensions are mandatory:

  • The RVA23S64 mandatory unprivileged extensions include all the mandatory unprivileged extensions in RVA23U64.

  • Zifencei Instruction-Fetch Fence.

Note
 Zifencei is mandated as it is the only standard way to support instruction-cache coherence in RVA23 application processors. A new instruction-cache coherence mechanism is under development (tentatively named Zjid) which might be added as an option in the future.

The following privileged extensions are mandatory:

  • Ss1p13 Supervisor architecture version 1.13.

Note
 Ss1p13 supersedes Ss1p12.

The following privileged extensions were also mandatory in RVA22S64:

  • Svbare The satp mode Bare must be supported.

  • Sv39 Page-based 39-bit virtual-Memory system.

  • Svade Page-fault exceptions are raised when a page is accessed when A bit is clear, or written when D bit is clear.

  • Ssccptr Main memory regions with both the cacheability and coherence PMAs must support hardware page-table reads.

  • Sstvecd stvec.MODE must be capable of holding the value 0 (Direct). When stvec.MODE=Direct, stvec.BASE must be capable of holding any valid four-byte-aligned address.

  • Sstvala stval must be written with the faulting virtual address for load, store, and instruction page-fault, access-fault, and misaligned exceptions, and for breakpoint exceptions that are defined to write an address to stval, other than those caused by execution of the EBREAK or C.EBREAK instructions. For virtual-instruction and illegal-instruction exceptions, stval must be written with the faulting instruction.

  • Sscounterenw For any hpmcounter that is not read-only zero, the corresponding bit in scounteren must be writable.

  • Svpbmt Page-based memory types

  • Svinval Fine-grained address-translation cache invalidation.

The following are new mandatory extensions:

  • Svnapot NAPOT translation contiguity.

Note
 Svnapot was optional in RVA22.

  • Sstc supervisor-mode timer interrupts.

Note
 Sstc was optional in RVA22.

  • Sscofpmf count overflow and mode-based filtering.

  • Ssnpm Pointer masking, with senvcfg.PMM and henvcfg.PMM supporting, at minimum, settings PMLEN=0 and PMLEN=7.

  • Ssu64xl sstatus.UXL must be capable of holding the value 2 (i.e., UXLEN=64 must be supported).

Note
 Ssu64xl was optional in RVA22.

  • Sha The augmented hypervisor extension.

Note
 Sha is a new profile-defined extension that captures the full set of features that are mandated to be supported along with the H extension. There is no change to the features added by including the hypervisor extension in a profile—​the new name is solely to simplify the text of the profiles. The definition has been added to the RVA22 profile text, where the hypervisor extension was first added, but will be added to the hypervisor section of the combined ISA manual.

Sha comprises the following extensions:

  • H The hypervisor extension.

  • Ssstateen Supervisor-mode view of the state-enable extension. The supervisor-mode (sstateen0-3) and hypervisor-mode (hstateen0-3) state-enable registers must be provided.

  • Shcounterenw For any hpmcounter that is not read-only zero, the corresponding bit in hcounteren must be writable.

  • Shvstvala vstval must be written in all cases described above for stval.

  • Shtvala htval must be written with the faulting guest physical address in all circumstances permitted by the ISA.

  • Shvstvecd vstvec.MODE must be capable of holding the value 0 (Direct). When vstvec.MODE=Direct, vstvec.BASE must be capable of holding any valid four-byte-aligned address.

  • Shvsatpa All translation modes supported in satp must be supported in vsatp.

  • Shgatpa For each supported virtual memory scheme SvNN supported in satp, the corresponding hgatp SvNNx4 mode must be supported. The hgatp mode Bare must also be supported.

Note
 The augmented hypervisor extension (exactly equivalent to Sha) was optional in RVA22.

RVA23S64 Optional Extensions

RVA23S64 has the same unprivileged options as RVA23U64.

The privileged options in RVA23S64 are listed in the following sections.

Localized Options

There are no privileged localized options in RVA23S64.

Development Options

There are no privileged development options in RVA23S64.

Expansion Options

The following privileged expansion options were present in RVA22S64:

  • Sv48 Page-based 48-bit virtual-memory system.

  • Sv57 Page-based 57-bit virtual-memory system.

  • Zkr Entropy CSR.

The following are new privileged expansion options in RVA23S64

  • Svadu Hardware A/D bit updates.

  • Sdtrig Debug triggers.

  • Ssstrict No non-conforming extensions are present. Attempts to execute unimplemented opcodes or access unimplemented CSRs in the standard or reserved encoding spaces raises an illegal instruction exception that results in a contained trap to the supervisor-mode trap handler.

Note
 Ssstrict is a new profile-defined extension that restricts the behavior of reserved encoding spaces. The extension will be added to the supervisor chapter of the privileged architecture.
Note
 Ssstrict does not prescribe behavior for the custom encoding spaces or CSRs.
Note
 Ssstrict definition applies to the execution environment claiming to be RVA23-compatible, which must have the hypervisor extension. That execution environment will take a contained trap to supervisor-mode (however that trap is implemented, including, but not limited to, emulation/delegation in the outer execution environment). Ssstrict (and all the other RVA23 mandates and options) do not apply to any guest VMs run by a hypervisor. An RVA23 hypervisor can provide guest VMs that are also RVA23-compatible but with an expanded set of emulated standard instructions. An RVA23 hypervisor can also choose to implement guest VMs that are not RVA23 compatible (e.g., lacking H, or only RVA20).

  • Svvptc Transitions from invalid to valid PTEs will be visible in bounded time without an explicit memory-management fence.

  • Sspm Supervisor-mode pointer masking, with the supervisor execution environment providing a means to select PMLEN=0 and PMLEN=7 at minimum.

Transitory Options

There are no privileged transitory options in RVA23S64.

RVA23S64 Recommendations

  • Implementations are strongly recommended to raise illegal-instruction exceptions when attempting to execute unimplemented opcodes or access unimplemented CSRs.

Glossary of ISA Extensions

The following unprivileged ISA extensions are defined in Volume I of the RISC-V Instruction Set Manual.

  • M Extension for Integer Multiplication and Division

  • A Extension for Atomic Instructions

  • F Extension for Single-Precision Floating-Point

  • D Extension for Double-Precision Floating-Point

  • H Hypervisor Extension

  • Q Extension for Quad-Precision Floating-Point

  • C Extension for Compressed Instructions

  • B Extension for Bit Manipulation

  • V Extension for Vector Computation

  • Zifencei Instruction-Fetch Fence Extension

  • Zicsr Extension for Control and Status Register Access

  • Zicntr Extension for Basic Performance Counters

  • Zihpm Extension for Hardware Performance Counters

  • Zihintpause Pause Hint Extension

  • Zfh Extension for Half-Precision Floating-Point

  • Zfhmin Minimal Extension for Half-Precision Floating-Point

  • Zfinx Extension for Single-Precision Floating-Point in x-registers

  • Zdinx Extension for Double-Precision Floating-Point in x-registers

  • Zhinx Extension for Half-Precision Floating-Point in x-registers

  • Zhinxmin Minimal Extension for Half-Precision Floating-Point in x-registers

  • Zba Address Computation Extension

  • Zbb Bit Manipulation Extension

  • Zbc Carryless Multiplication Extension

  • Zbs Single-Bit Manipulation Extension

  • Zk Standard Scalar Cryptography Extension

  • Zkn NIST Cryptography Extension

  • Zknd AES Decryption Extension

  • Zkne AES Encryption Extension

  • Zknh SHA2 Hashing Extension

  • Zkr Entropy Source Extension

  • Zks ShangMi Cryptography Extension

  • Zksed SM4 Block Cypher Extension

  • Zksh SM3 Hashing Extension

  • Zkt Extension for Data-Independent Execution Latency

  • Zicbom Extension for Cache-Block Management

  • Zicbop Extension for Cache-Block Prefetching

  • Zicboz Extension for Cache-Block Zeroing

  • Zawrs Wait-on-reservation-set instructions

  • Zacas Extension for Atomic Compare-and-Swap (CAS) instructions

  • Zabha Extension for Byte and Halfword Atomic Memory Operations

  • Zbkb Extension for Bit Manipulation for Cryptography

  • Zbkc Extension for Carryless Multiplication for Cryptography

  • Zbkx Crossbar Permutation Extension

  • Zvbb - Vector Basic Bit-manipulation

  • Zvbc - Vector Carryless Multiplication

  • Zvkng - NIST Algorithm Suite with GCM

  • Zvksg - ShangMi Algorithm Suite with GCM

  • Zvkt - Vector Data-Independent Execution Latency

The following privileged ISA extensions are defined in Volume II of the RISC-V Instruction Set Manual.

  • Sv32 Page-based Virtual Memory Extension, 32-bit

  • Sv39 Page-based Virtual Memory Extension, 39-bit

  • Sv48 Page-based Virtual Memory Extension, 48-bit

  • Sv57 Page-based Virtual Memory Extension, 57-bit

  • Svpbmt, Page-Based Memory Types

  • Svnapot, NAPOT Translation Contiguity

  • Svinval, Fine-Grained Address-Translation Cache Invalidation

  • Hypervisor Extension

  • Sm1p11, Machine Architecture v1.11

  • Sm1p12, Machine Architecture v1.12

  • Ss1p11, Supervisor Architecture v1.11

  • Ss1p12, Supervisor Architecture v1.12

  • Ss1p13, Supervisor Architecture v1.13

  • Sstc Extension for Supervisor-mode Timer Interrupts

  • Sscofpmf Extension for Count Overflow and Mode-Based Filtering

  • Smstateen/Ssstateen Extension for State-enable

  • Svvptc Obviating Memory-management Instructions after Marking PTEs valid

  • Svadu Hardware Updating of A/D Bits

The following extensions have not yet been incorporated into the RISC-V Instruction Set Manual; the hyperlinks lead to their separate specifications.